1. Field of the Invention
The subject method and system for automatically optimizing physical implementation of an electronic circuit is generally directed to the hardware implementation of a schematically defined electronic circuit. More specifically, the method and system automatically optimize certain aspects of the circuit's physical implementation based upon automatic analysis of its simulated operation.
To carry out such electronic circuit physical implementations as printed circuit boards (PCBs), the general design flow illustrated in FIG. 1 is typically followed. Once the desired electronic circuit is conceptually designed, it is schematically defined at the design entry stage 2. The schematic definition includes functional representations of electronic components and/or devices interconnected at various nodes by appropriate nets.
The functional integrity of this schematically defined circuit is then tested at the simulation stage 4. As the circuit has not been physically implemented at this stage, its electrical response is tested under simulated operational conditions, and the results analyzed by the user to assess the design's operability. The physical constraints that may be imposed by such factors as excessive voltage and current levels, power dissipation capacity, and potential electromagnetic interference (EMI) indicated by simulation remain to be addressed following this stage. Particularly in power electronics applications where voltage and current levels, their rates of change, power dissipation capacity of components, and potential EMI are sufficient in degree to significantly impact such implementation constraints as clearances between interconnection tracks, track widths, track lengths, and the placement of components. Reliability, safety, and adherence to performance standards will typically depend very much on the degree to which these constraints are optimized and observed, in light of the available resources.
Referring back to FIG. 1, the typical approach heretofore has been for the designer to manually intervene to analyze quantitative results obtained from the simulation in light of the prevailing implementation factors and formulate the appropriate constraints to be applied at the board placement & routing stage 6. The designer applies his/her expertise the simulation results to identify EMI critical nets, tracks requiring broader spacing, connections carrying high currents, components running at high temperatures, and the like. The designer then applies the appropriate board layout rules to the identified circuit portions and pertinent electrical quantities, manually imposing constraints upon the PCB routing that is to occur.
While automated tools may be utilized by the designer for one or more steps in this process, the overall approach remains quite manually coordinated and controlled, making the task of optimizing the constraints responsive extremely difficult. Indeed, even with the most skilled of designers and meticulous calculations, too many numeric iterations would be required to effectively optimize the implementation constraints in this manner. The calculations, in many cases, would yield at best approximations that fail to fully account for operational factors like the voltage and current conditions during operation over an entire time-point continuum.
The shear number of manual calculations and estimations alone would be overwhelming enough in many applications to keep the manually driven approach from being other than highly approximate in nature. For example, a circuit having a total of n nets would require n evaluations of currents and n*(n−1)/2 evaluations of estimated voltage differences across all net pairs. Comprehensive manual evaluation of the entire circuit very quickly becomes an unmanageable task, where the circuit even remotely approaches marginal levels of complexity.
Numerous undesirable consequences thus result from the highly manual approach to determining and applying appropriate implementation constraints, particularly in power electronic applications. Longer design cycles are brought about. Designers are forced to choose between accuracy and burdensome calculations, one at the expense of the other. Sub-optimal circuit implementations are made due to constraints based upon quantitative approximations such factors invariably conspire to raise manufacturing costs.
Perhaps even more significantly, much of the quantitative results made available by simulation remain largely unexploited in determining board layout. This is all the more problematic given that many simulation tools presently available, such as the SPICE simulation system, provide highly accurate modeling of a circuit's response during both transient and steady state operational periods. The growing levels of complexity in electronic circuit designs, in the meantime, invariably require increasingly tedious iterations to formulate implementation constraints at some appreciable degree of optimization. This makes it virtually impossible in many cases to adequately formulate constraints covering the entirety of the given circuit's implementation layout, much less over the full range of pertinent operational time periods, using the approaches heretofore employed.
2. Prior Art
Techniques for minimizing the computational burden in formulating layout constraints for PCB implementation of electronic circuits are known in the art. For example, spreadsheets containing correlations between trace widths and electric current values have been employed by circuit designers to aid them in setting particular trace widths for a circuit layout. Spreadsheets containing correlations between certain track clearance measures with particular voltage values have similarly been employed by circuit designers. Still, there is no method or system heretofore known which formulates and applies a set of implementation constraints comprehensibly optimized for substantially the entire circuit, over substantially the full range of its pertinent operational time periods. There is a need, moreover, for such a method and system which automatically formulates and applies the optimized implementation constraints automatically based upon voltages, currents, and/or other such actual measurements obtained from simulated operation of the circuit.